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Makefile: use += to append to variables

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yenatch 2013-12-08 18:02:29 -05:00
parent 493b483490
commit b9218d843b
1 changed files with 1 additions and 1 deletions
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2
Makefile
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@ -18,7 +18,7 @@ $(shell $(foreach obj, $(OBJS), \
$(eval $(obj:.o=)_DEPENDENCIES := $(shell $(PYTHON) extras/pokemontools/scan_includes.py $(obj:.o=.asm) | sed s/globals.asm//g)) \ $(eval $(obj:.o=)_DEPENDENCIES := $(shell $(PYTHON) extras/pokemontools/scan_includes.py $(obj:.o=.asm) | sed s/globals.asm//g)) \
)) ))
$(shell $(foreach obj, $(OBJS), \ $(shell $(foreach obj, $(OBJS), \
$(eval ALL_DEPENDENCIES := $(ALL_DEPENDENCIES) $($(obj:.o=)_DEPENDENCIES)) \ $(eval ALL_DEPENDENCIES += $($(obj:.o=)_DEPENDENCIES)) \
)) ))
all: $(ROMS) all: $(ROMS)